ECE :: Digital Electronics
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Typical switching time for ECL is
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For a logic family
VOH is the minimum output high level voltage- VOL is the maximum output low level voltage
- VIH is the minimum acceptable input high level voltage
- VIL is the maximum acceptable input low level voltage
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How many and what are the machine cycles needed for execution of MOV D, C?
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The output data lines of microprocessor and memories are usually tristated because
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In the NMOS inverter
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A counter displays a sequence of numbers. If a reading corresponds to the hexadecimal number F52E, the next two readings are respectively
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A.
more than one device can transmit information over the data bus by enabling only one device at a time
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B.
more than one device can transmit information over the data bus at the same time
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C.
the data lines can be multiplexed for both I/P and O/P
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D.
it increases the speed of data transfers over the data bus
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