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ECE :: Digital Electronics

Digital Electronics - Section 1
Digital Electronics - Section 2
Digital Electronics - Section 3
Digital Electronics - Section 4
Digital Electronics - Section 5
Digital Electronics - Section 6
Digital Electronics - Section 7
Digital Electronics - Section 8
Digital Electronics - Section 9
Digital Electronics - Section 10
Digital Electronics - Section 11
Digital Electronics - Section 12
Digital Electronics - Section 13
Digital Electronics - Section 14
Digital Electronics - Section 15
Digital Electronics - Section 16
Digital Electronics - Section 17
Digital Electronics - Section 18
Digital Electronics - Section 19
Digital Electronics - Section 20
Digital Electronics - Section 21
Digital Electronics - Section 22
Digital Electronics - Section 23
Digital Electronics - Section 24
Digital Electronics - section-25
Digital Electronics - Section-26

  1. For an N bit ADC, the percentage resolution is [1/2N - 1)] 100.

    2. A.
    True
    B.
    False

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  2. Commercial ECL gates use two ground lines and one negative supply to

    3. A.
    reduce power consumption
    B.
    increase fan out
    C.
    reduce loading effect
    D.
    eliminate the effect of power line glitches on the biasing circuit

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  3. Dynamic memory cells are constructed using

    4. A.
    FETs
    B.
    MOSFETs
    C.
    Transistors
    D.
    Flip flops

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  4. Which of the following is incorrect?

    5. A.
    (8)16 = (8)8
    B.
    (5)16 = (5)8
    C.
    (8)2 = (2)10
    D.
    (2)16 = (2)10

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  5. A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q0 Q1 Q2 = 101. The frequency of output Q0 Q1 Q2 will be

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  6. A depletion type NMOS is operated in enhancement mode. Vp = - 4 volts. For VGS = + 3 volts as VDS is increased, ID becomes nearly constant when Vps equals

    7. A.
    1 volt
    B.
    3 volts
    C.
    4 volt
    D.
    7 volts

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  7. Which one of the following is D/A conversion technique?

    8. A.
    Successive approximation
    B.
    Weighted resistor
    C.
    Dual slope
    D.
    Single slope

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  8. Assuming accumulator contain A 64 and the carry is set (1). What will accumulator (A) and carry (CY) contain after ANA A?

    9. A.
    A 6 H, 1
    B.
    A 6 H, 0
    C.
    00 H, 0
    D.
    00 H, 1

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  9. A number is expressed in binary 2's complement as 10011 decimal equivalent value is

    10. A.
    19
    B.
    13
    C.
    -19
    D.
    -13

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  10. In INHIBIT operation

    11. A.
    output is 1 when both inputs are 0
    B.
    output is 0 when blocking input is 1
    C.
    output is 0 when blocking input is 0
    D.
    output is 1 when blocking input is either 0 or 1

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