Microprocessors - ECE Questions and Answers

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Which of the following depends on the microprocessor speed

Clock

Data Bus Width

Address Bus Width

Size of Register

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In 8088, which of the following option differs from 8086

Data width on the output

Supports Co-processor

Address capability

Supports max/min mode

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In 8255, ______number of modes of I/O mode of operation we have, which of the following features comes under which mode

(i) A 5 bit control port is available.

(ii) 3 I/O lines are available at Port C

3, Mode2

2, Mode2

4, Mode3

3, Mode2

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In ADC 0808, which of the following pin enables high output

EOC

I/P0-I/P7

SOC

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In 8279 status word, when data is read then which of the following pins are set to low, & in write to the display RAM then which of the following pins are set to low

Ao, CS, RD & Ao, CS, WR

Ao, CS, WR & Ao, CS, RD

Ao, RD & CS, WR

CS, RD & Ao, CS

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Normally 8279 provides a maximum of _____ seven segment display interface with CPU

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When 8086 microprocessor is interfaced to 8253 a programmable interval timer. Then the maximum number by which the clock frequency on one of the timers is divided by ____

2¹⁶

2⁸

2¹⁰

2²⁰

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When 8086 is interfaced to two 8259s (Programmable interrupt controllers) & 8259's are in master slave configuration then the number of interrupts available to the 8086 microprocessor are ______

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In which of the following T-state does the CPU sends the address to memory or I/O & ALE signal for demultiplexing