GATE 2017-2018 :: GATE CSE
- Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, ...., I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is
- A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
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The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.c = a + b;d = c * a;e = c + a;x = c * c;if (x > a) {y = a * a;}else {d = d * d;e = e * e;}What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.
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The procedure given below is required to find and replace certain characters inside an input character string supplied in array A. The characters to be replaced are supplied in array oldc, while their respective replacement characters are supplied in array newc. Array A has a fixed length of five characters, while arrays oldc and newc contain three characters each. However, the procedure is flawed. void find_and_replace (char *A, char *oldc, char *newc) {for (int i=0; i<5; i++)for (int j=0; j<3; j++)if (A[i] == oldc[j]) A[i] = newc[j];}The procedure is tested with the following four test cases.(1) oldc = "abc, newc = "dab (2) oldc = "cde, newc = "bcd(3) oldc = "bca, newc = "cda (4) oldc = "abc, newc = "bacThe tester now tests the program on all input strings of length five consisting of characters 'a', 'b', 'c', 'd' and 'e' with duplicates allowed. If the tester carries out this testing with the four test cases given above, how many test cases will be able to capture the flaw?
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The procedure given below is required to find and replace certain characters inside an input character string supplied in array A. The characters to be replaced are supplied in array oldc, while their respective replacement characters are supplied in array newc. Array A has a fixed length of five characters, while arrays oldc and newc contain three characters each. However, the procedure is flawed. void find_and_replace (char *A, char *oldc, char *newc) {for (int i=0; i<5; i++)for (int j=0; j<3; j++)if (A[i] == oldc[j]) A[i] = newc[j];}The procedure is tested with the following four test cases.(1) oldc = "abc, newc = "dab (2) oldc = "cde, newc = "bcd(3) oldc = "bca, newc = "cda (4) oldc = "abc, newc = "bacIf array A is made to hold the string "abcde, which of the above four test cases will be successful in exposing the flaw in this procedure?
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A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?
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A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?
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Relation R has eight attributes ABCDEFGH. Fields of R contain only atomic values. F={CH→G, A→BC, B→CFH, E→A, F→EG} is a set of functional dependencies (FDs) so that F+ is exactly the set of FDs that hold for R.How many candidate keys does the relation R have?
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Relation R has eight attributes ABCDEFGH. Fields of R contain only atomic values. F={CH→G, A→BC, B→CFH, E→A, F→EG} is a set of functional dependencies (FDs) so that F+ is exactly the set of FDs that hold for R.The relation R is
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Which one of the following options is the closest in meaning to the word given below? Nadir
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