Network Analysis and Synthesis - ECE Questions and Answers

Home / ECE / Network Analysis and Synthesis :: Discussion

In the circuit of figure

V_a would always lag V_b

V_a would always lead V_b

V_a and V_b would always be in phase

V_a may lag or lead V_b

Answer : Option B

Explanation :

Voltage across inductance leads the current and voltage across resistance is in phase with the current.

Be The First To Comment

Comments

Name