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Discussion :: Network Analysis and Synthesis

  1. In the circuit of figure is

    2. A.
    I1 will always lag I3
    B.
    I2 may be in phase or lag I3
    C.
    I3 will always lag I2
    D.
    I2 and I3 will be in phase

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    Answer : Option C

    Explanation :

    I3 is inductive current and must lag I2 which is capacitive current.

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