Discussion :: Exam Questions Paper
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For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible
Which of the following statements is true?
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A.
Q goes to 1 to the CLK transition and stays at 1
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B.
Q goes to 0 at the CLK transition and stays at 10
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C.
Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
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D.
Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
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Answer : Option C
Explanation :
No answer description available for this question.
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