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Discussion :: Digital Electronics

  1. In a clocked NAND latch, race condition occur when

    2. A.
    R and S are high CLK is low
    B.
    R and CLK are high and S is low
    C.
    R, S, CLK are high
    D.
    R, S, CLK are low

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    Answer : Option C

    Explanation :

    No answer description available for this question.

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